1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and its fabrication method, and more particularly, to an LCD device employing a thin film transistor (TFT) having a top gate structure and simplified fabrication method that reduces the number of masks used to fabricate the TFT.
2. Background of the Related Art
The demand for portable information display devices has been increasing rapidly, resulting in the active research and development for the thin flat panel displays (FPD). These thin FPDs are replacing the CRT (Cathode Ray Tube) today. Among the FPDs, the LCD device has been used widely in the notebook computer, desktop monitors, or the like because the LCD device offers an excellent color, high resolution, and better picture quality. Typically, the LCD device displays images by controlling the optical anisotropy of liquid crystal molecules.
The liquid crystal display panel includes a first substrate (a color filter substrate) and a second substrate (an array substrate), and a liquid crystal layer is formed between the color filter substrate and the array substrate. In the LCD device, a thin film transistor (TFT) is commonly used as a switching device. An amorphous silicon thin film or a polycrystalline silicon thin film may be used as a channel layer of the TFT. In fabricating the LCD device, a plurality of masking processes or photolithography processes are required to fabricate the LCD device including the TFT. Accordingly, when the number of masking processes is reduced, it helps increase the production yield.
The structure of a related art LCD device will now be described with reference to FIG. 1. FIG. 1 is a plan view showing a portion of an array substrate of the related art LCD device. Although actual LCD devices include M×N pixels as the N gate lines cross the M data lines, only one pixel is shown in FIG. 1 for convenience.
As shown, a gate line 16 is arranged in horizontal direction and a data line 17 is arranged in vertical direction on an array substrate 10. A pixel region is defined by the intersections of the gate line 16 and the data line 17. A TFT (a switching device) is formed at an intersection of the gate line 16 and the data line 17. A pixel electrode 18 is formed in each pixel region. The TFT includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. The TFT also includes a first insulation film (not shown) and a second insulation film (not shown) for insulating the gate electrode 21 from the source/drain electrodes 22 and 23, and an active area 24 that forms a conductive channel between the source and drain electrodes 22 and 23 when a gate voltage is supplied to the gate electrode 21.
The first contact holes 40A are formed through the first and second insulation films, and the source electrode 22 is electrically connected with a source region of the active area 24 within one of the first contact hole 40A. Similarly, the drain electrode 23 is electrically connected with a drain region of the active area 24 within the other first contact hole 40A. A third insulation film (not shown) having a second contact hole 40B is formed on the drain electrode 23, so that the drain electrode 23 and the pixel electrode 18 are electrically connected within the second contact hole 40B.
The process of fabricating the array substrate as described above will now be explained with reference to FIGS. 2A to 2H. FIGS. 2A to 2H are sectional views taken along line I-I′ of FIG. 1 illustrating the fabrication process of the array substrate of FIG. 1. The TFT is formed as an amorphous silicon TFT which uses the amorphous silicon as a channel layer. In addition, the amorphous silicon TFT includes a TFT having a top gate structure in which a gate electrode is formed over the portion of the channel layer.
As shown in FIG. 2A, an amorphous silicon thin film 20 and n+ amorphous silicon thin film 30 are sequentially formed on a substrate 10. Thereafter, as shown in FIG. 2B, the amorphous silicon thin film 20 and the n+ amorphous silicon thin film 30 are selectively patterned to form an active layer 20′ and n+ amorphous silicon thin film pattern 30′. The n+ amorphous silicon thin film pattern 30′ remains on the active layer 20′.
Next, as shown in FIG. 2C, the n+ amorphous silicon pattern 30′ is selectively patterned by a photolithography process (a second masking process) to form a first ohmic contact layer 30A and a second ohmic contact layer 30B.
Then, as shown in FIG. 2D, a first insulation film 15A and a conductive metallic material are sequentially deposited on the entire surface of the substrate 10 where the active layer 20′ has been formed. Thereafter, the conductive metallic material is selectively patterned by the photolithography process (a third masking process) to form a gate electrode 21 over the portion of the active layer 20′.
Next, as shown in FIG. 2E, a second insulation film 15B is deposited on the entire surface of the substrate 10 including the gate electrode 21. Then, a portion of the first and second insulation films 15A and 15B are removed through the photolithography process (a fourth masking process) to form a pair of first contact holes 40A exposing a portion of the ohmic contact layers 30A and 30B.
And, as shown in FIG. 2F, a conductive metallic material is deposited on the entire surface of the substrate 10 and patterned by the photolithography process (a fifth masking process) to form source electrode 22 and a drain electrode 23. The source electrode 22 electrically connects with the first ohmic contact layer 30A within the first contact hole 40A. Similarly, the drain electrode 23 electrically connects with the second ohmic contact layer 30B within the first contact holes 40A. And, a portion of the conductive metallic layer constituting the source electrode 22 extends in one direction to form a data line 17.
Subsequently, as shown in FIG. 2G, a third insulation film 15C is deposited on the entire surface of the substrate 10 and then patterned by the photolithography process (a sixth masking process) to form a second contact hole 40B exposing a portion of the drain electrode 23.
Finally, as shown in FIG. 2H, a transparent conductive metallic material is deposited on the entire surface of the substrate 10 including the third insulation film 15C, and patterned by the photolithography process (a seventh masking process) to form a pixel electrode 18. The pixel electrode 18 electrically connects with the drain electrode 23 within the second contact hole 40B.
As mentioned above, there are total of seven (7) photolithography processes required to fabricate the related art array substrate including the TFT having the top gate structure. The seven (7) photolithography processes are needed to pattern the active layer, the ohmic contact layer, the gate electrode, the first contact hole, the source/drain electrodes, the second contact hole and the pixel electrode.
The photolithography process transfers a pattern formed on a mask onto a thin film deposited on a substrate, thereby forming a desired pattern. Some of the typical photolithography process includes an application of photosensitive solution, exposing, and developing processes. As a result, these photolithography processes reduce the production yield and increase the possibility that a fabricated TFT is defective.
In addition, the masks designed to form the pattern are expensive such that when more masks are used in the fabricating process, the fabrication cost increases.